PIC18F13K50-I/MQ【PDF 21/285 页】IC PIC MCU FLASH 512KX8 20-QFN

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Sheet目录3877

17页 18页 19页 20页 [21页]22页 23页 24页 25页

2010 Microchip Technology Inc.

Preliminary

DS41350E-page 117

PIC18F/LF1XK50

14.0

ENHANCED

CAPTURE/COMPARE/PWM

(ECCP) MODULE

PIC18F/LF1XK50

devices

have

one

ECCP

(Capture/Compare/PWM)

module.

The

module

contains a 16-bit register which can operate as a 16-bit

Capture register, a 16-bit Compare register or a PWM

Master/Slave Duty Cycle register.

CCP1 is implemented as a standard CCP module with

enhanced PWM capabilities. These include:

Provision for 2 or 4 output channels

Output steering

Programmable polarity

Programmable dead-band control

Automatic shutdown and restart.

The enhanced features are discussed in detail in

Section 14.4 “PWM (Enhanced Mode)”.

REGISTER 14-1:

CCP1CON: ENHANCED CAPTURE/COMPARE/PWM CONTROL REGISTER

R/W-0

P1M1

P1M0

DC1B1

DC1B0

CCP1M3

CCP1M2

CCP1M1

CCP1M0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

P1M<1:0>: Enhanced PWM Output Configuration bits

If CCP1M<3:2> = 00, 01, 10:

= P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins

If CCP1M<3:2> = 11:

= Single output: P1A, P1B, P1C and P1D controlled by steering (See Section 14.4.7 “Pulse Steering

Mode”).

= Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive

= Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins

= Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive

bit 5-4

DC1B<1:0>: PWM Duty Cycle bit 1 and bit 0

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in

CCPR1L.

bit 3-0

CCP1M<3:0>: Enhanced CCP Mode Select bits

0000

= Capture/Compare/PWM off (resets ECCP module)

0001

= Reserved

0010

= Compare mode, toggle output on match

0011

= Reserved

0100

= Capture mode, every falling edge

0101

= Capture mode, every rising edge

0110

= Capture mode, every 4th rising edge

0111

= Capture mode, every 16th rising edge

1000

= Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF)

1001

= Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF)

1010

= Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state

1011

= Compare mode, trigger special event (ECCP resets TMR1 or TMR3, start A/D conversion, sets

CC1IF bit)

1100

= PWM mode; P1A, P1C active-high; P1B, P1D active-high

1101

= PWM mode; P1A, P1C active-high; P1B, P1D active-low

1110

= PWM mode; P1A, P1C active-low; P1B, P1D active-high

1111

= PWM mode; P1A, P1C active-low; P1B, P1D active-low

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